1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device having asymmetric source/drain regions by employing a semiconductor layer having a mesa structure.
2. Description of the Related Art
As semiconductor devices continue to become more integrated to an ever-increasing degree, the area occupied by a unit memory cell of the semiconductor device is continuously reduced. For example, a metal oxide semiconductor field effect transistor (MOSFET) may include a gate electrode having dimensions on the order of nanometers. With this in mind, photolithography processes have been developed to precisely form a minute gate electrode using X-ray energy. However, such an apparatus for performing the photolithography process may have a complicated construction, and time and cost for manufacturing a MOSFET under these conditions may be considerably augmented. Additionally, when the minute gate electrode of the MOSFET is formed by the photolithography process, the MOSFET can be subject to a short channel effect such as a punch through phenomenon or a drain induced barrier lowering phenomenon although the MOSFET may have an increased saturation current (Idsat) to improve a response speed thereof.
Considering the above-mentioned problem, a conventional transistor including asymmetric lightly doped source/drain regions is reported by “Asymmetric Source/Drain Extension Transistor Structure for High Performance Sub-50 nm Gate Length CMOS Device (2001 Symposium on VLSI Technology Digest of Technical Papers).” In the conventional transistor having the asymmetric lightly doped source/drain regions, because the lightly doped drain region has a length and a width respectively shorter and narrower than those of the lightly doped source region, the transistor has an increased saturation current (Idsat) and also prevents or mitigates the occurrence of the short channel effect.
However, when the asymmetric source/drain regions of the transistor are formed at portions of a substrate by a tilted angle ion implantation process, an undesired offset region may be generated adjacent to the source/drain regions as follows.
FIG. 1 is a cross sectional view illustrating a conventional method of manufacturing a transistor that includes asymmetric lightly doped source/drain regions.
Referring to FIG. 1, a gate electrode 15 is formed on a semiconductor substrate 10. Impurities are implanted into portions of the substrate 10 adjacent to the gate electrode 15 by a perpendicular ion implantation process 20 and a tilted angle ion implantation process 25, thereby forming asymmetric lightly doped source and drain regions 30 and 35 at the portions of the substrate 10.
However, since the gate electrode 15 may obstruct implantations of impurities in the tilted angle ion implantation process 25, a serious offset region 40 may be formed at a portion of the substrate 10 between the gate electrode 15 and the lightly doped drain region 35, thereby causing the short channel effect in the transistor.